1. Field of the Invention
The present invention relates to an integrating circuit internally included in a semiconductor device, and more specifically to an integrating circuit having an improved precision in an integral time.
2. Description of Related Art
An integrating circuit internally included in a semiconductor device is used for example as one of timer circuits provided in a microcomputer. Referring to FIG. 1, there is shown a block diagram showing one example of the prior art integrating circuit.
The shown integrating circuit includes an input terminal IN for receiving a signal VIN to be measured, a connection terminal CPT to which an integrating capacitor (not shown) is to be externally connected, a constant voltage circuit 41 for generating a predetermined constant voltage VREF, a voltage-to-current converting circuit 42 for converting the voltage VREF of the constant voltage circuit 41 into a current IREF or I0, which is supplied to the capacitor (not shown) externally connected to the connection terminal CPT. In order to detect an integral potential charged in the capacitor (not shown) connected to the connection terminal CPT, the shown integrating circuit also includes a voltage comparator 43 having one input connected to the capacitor connection terminal CPT and the other input connected to the input terminal IN, to compare both input voltages and to invert its output voltage to an output terminal OUT when both the input voltages becomes consistent with each other. Furthermore, the shown integrating circuit includes an NPN transistor NSW having a collector connected to the capacitor connection terminal CPT and an emitter connected to ground, and so configured to be brought into either a saturated conductive condition or a cutoff condition, in response to a control voltage VCTL supplied to a base of the transistor, and a control circuit 44 connected to a control terminal CTL for supplying the control voltage VCTL to the base of the transistor NSW in accordance with a control signal externally supplied to the control terminal CTL.
Referring to FIG. 2, there is shown a timing chart illustrating an operation of the prior art integrating circuit shown in FIG. 1. If the control circuit 44 is externally controlled through the control terminal CTL, the control voltage signal VCTL outputted from the control circuit 44 is caused to change from a logical low level to a logical high level at a timing t=t.sub.0. In response to this level change of the control voltage signal VCTL, the transistor NSW is brought from the saturated conductive condition into the cutoff condition. As a result, the output current I0 of the constant current outputted from the voltage-to-current converting circuit 42 starts to be supplied through the connection terminal CPT to the capacitor (not shown), so that the capacitor starts to be charged.
A charged potential VC of the capacitor gradually elevates. As a result, at a timing t=t.sub.1 where the charged potential VC reaches the voltage VIN to be measured which is a target for comparison, the output of the voltage comparator 43 inverts so that a high level is outputted to the output terminal OUT. On the other hand, the charged potential VC continues to elevate without dropping, and if the charged potential VC reaches the output potential of the voltage-to-current converting circuit 42, the charged potential Vc continues to maintain the output potential of the voltage-to-current converting circuit 42.
Here, assuming that a length of time from the moment (t.sub.0) the control voltage signal VCTL changed from the low level to the high level to the moment (t.sub.1) the output of the voltage comparator 43 changed from the low level to the high level, is "T", a capacitance of the capacitor is "C", and a collector-emitter voltage of the transistor NSW in the saturated conductive condition is "VCEsat", T can be expressed as follows: EQU T=C.times.(VIN-VCEsat)/I0 (1)
Namely, the magnitude of the potential of the signal VIN to be measured can be grasped as the length of time T.
In the prior art integrating circuit as mentioned above, however, the saturation voltage VCEsat of the transistor NSW is involved in precision of the integral time. But, not only the saturation voltage of the transistor NSW is influenced by variation in diffusion in a manufacturing process, but also it has a temperature dependency. Therefore, in order to elevate the precision of the integrating circuit, the size of the transistor NSW must be enlarged.
However, this is disadvantageous, because enlargement of the transistor size in order to elevate the precision of the integrating circuit, is contrary to the trend of semiconductor devices in which the semiconductor device is further microminiaturized and the integration density is further elevated with advancement of micro-fabrication in the semiconductor manufacturing process.